The present application claims priority from Korean Application Serial No. 2001-0019946 filed Apr. 13, 2001, the disclosure of which is incorporated herein by reference as if set forth fully herein.
The present invention relates to semiconductor devices, and more particularly, to data paths of semiconductor memory devices.
A semiconductor memory device, especially a synchronous dynamic random access memory (SDRAM), is synchronized with a clock signal and stores data in a memory bank or outputs data in response to externally input address signals and command signals. In general, the SDRAM has more than two memory banks for storing data and is arranged symmetrically with control circuits for controlling operations of the memory banks. The externally input signals and data are transmitted to the memory banks through input pads and the control circuits, and data output from the memory banks are output to the SDRAM through the control circuits and output pads.
The address signals and command signals are externally applied to the memory banks through the input pads and the control circuits so that the data stored in the memory banks may be read. Then the data stored in the memory banks are output through the control circuits and the output pads.
Likewise, as the control circuits are arranged in the center of the memory banks, circuit arrangement and/or simulation may be simplified. However, when the data stored in the memory banks are read, the data stored in the memory banks, typically, must pass through the control circuits arranged in the center of the memory banks and be output through the output pads. Thus, data read times may be delayed. While conventional techniques may provide for increasing the capacity of the semiconductor memory device and/or operational speed may be improved, delay of the data read time may hinder high speed operation of the semiconductor memory device.
Embodiments of the present invention provide semiconductor memory devices having first and second memory banks for storing data, output pads arranged adjacent to the second memory bank and a control circuit arranged adjacent to the first memory bank for controlling operation of the first memory bank in response to an external control signal. A first output circuit is arranged adjacent to the first memory bank for transmitting data output from the first memory bank to the output pads in response to an output signal of the control circuit. A second output circuit is arranged adjacent to the second memory bank for transmitting data output from the second memory bank to the output pads in response to the output signal of the control circuit.
In further embodiments of the present invention, input pads are arranged adjacent to the first memory bank for transmitting the external control signal to the control circuit. The external control signal may include an address signal and a command signal. Furthermore, the control circuit may include a column address generator for generating a column address signal to select columns of the first and second memory banks. Row decoders for decoding a row address output from the control circuit and column decoders for decoding a column address output from the control circuit may also be arranged adjacent to the first and second memory banks.
In additional embodiments of the present invention, the first and second output circuits include an input/output sense amplifying unit for sensing and amplifying input and output data. The first and second output circuits may also include a multiplexing unit for controlling data output from the first and second memory bank, respectively, to be transmitted to the output pads in response to the output signal of the control circuit.
In particular embodiments of the present invention, the time taken for the control signal to access a plurality of memory cells included in the first memory bank is faster than the time taken for the control signal to access a plurality of memory cells included in the second memory bank. Furthermore, the time taken for the data output from the second memory bank to reach the output pads may be faster than the time taken for the data output from the first memory bank to reach the output pads. The path taken by the output signal of the control circuit to access the plurality of memory cells included in the first memory bank added to the path taken by the data output from the first memory bank and transmitted to the output pads may have the same or similar length to the path taken by the output signal to access the plurality of memory cells included in the second memory bank added to the path taken by the data output from the second memory bank and transmitted to the output pads.
In further embodiments of the present invention, the semiconductor memory device is a synchronous dynamic random access memory (SDRAM) operating in synchronization with a clock signal.
In still further embodiments of the present invention, read access to a first and a second memory bank of a semiconductor memory device having a control circuit for providing control signals to the first and second memory banks and output pads for output data from the first and second memory banks is provided by arranging the control circuit and the output pads with respect to the first and second memory banks such that a first difference between a time taken to provide control signals to the first memory bank and a time taken to provide control signals to the second memory bank is compensated for by a second difference between a time taken to provide data to the output pads from the second memory bank and a time taken to provide data to the output pads from the first memory bank.
Such an arrangement may be provided by locating the control circuit adjacent the first memory bank a first distance that is less than a distance from the control circuit to the second memory bank and locating the output pads adjacent the second memory bank a second distance that is less than a distance from the output pads to the first memory bank. Furthermore, the first distance and the second distance may be substantially the same. The first distance and the second distance may be selected such that the first difference and the second difference are substantially the same.
In still further embodiments of the present invention, a semiconductor memory device includes a first memory bank and a second memory bank. A control circuit is provided adjacent the first memory bank which controls read operations for both the first and the second memory banks. Output pads are provided adjacent the second memory bank for outputting data from the first and the second memory banks. The location of the control circuit and the location of the output pads provides substantially the same transmission delay for control signals from the control circuit to the second memory bank as for data output signals from the first memory bank to the output pads.